328 lines
7.3 KiB
C
328 lines
7.3 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __PHYDMDIG_H__
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#define __PHYDMDIG_H__
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#define DIG_VERSION "1.8" /*2015.07.01*/
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/* Pause DIG & CCKPD */
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#define DM_DIG_MAX_PAUSE_TYPE 0x7
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typedef struct _Dynamic_Initial_Gain_Threshold_
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{
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BOOLEAN bStopDIG; // for debug
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BOOLEAN bIgnoreDIG;
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BOOLEAN bPSDInProgress;
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u1Byte Dig_Enable_Flag;
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u1Byte Dig_Ext_Port_Stage;
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int RssiLowThresh;
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int RssiHighThresh;
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u4Byte FALowThresh;
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u4Byte FAHighThresh;
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u1Byte CurSTAConnectState;
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u1Byte PreSTAConnectState;
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u1Byte CurMultiSTAConnectState;
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u1Byte PreIGValue;
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u1Byte CurIGValue;
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u1Byte BackupIGValue; //MP DIG
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u1Byte BT30_CurIGI;
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u1Byte IGIBackup;
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s1Byte BackoffVal;
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s1Byte BackoffVal_range_max;
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s1Byte BackoffVal_range_min;
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u1Byte rx_gain_range_max;
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u1Byte rx_gain_range_min;
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u1Byte Rssi_val_min;
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u1Byte PreCCK_CCAThres;
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u1Byte CurCCK_CCAThres;
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u1Byte PreCCKPDState;
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u1Byte CurCCKPDState;
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u1Byte CCKPDBackup;
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u1Byte pause_cckpd_level;
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u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
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u1Byte LargeFAHit;
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u1Byte ForbiddenIGI;
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u4Byte Recover_cnt;
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u1Byte DIG_Dynamic_MIN_0;
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u1Byte DIG_Dynamic_MIN_1;
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BOOLEAN bMediaConnect_0;
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BOOLEAN bMediaConnect_1;
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u4Byte AntDiv_RSSI_max;
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u4Byte RSSI_max;
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u1Byte *bP2PInProcess;
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u1Byte pause_dig_level;
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u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
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#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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BOOLEAN bTpTarget;
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BOOLEAN bNoiseEst;
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u4Byte TpTrainTH_min;
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u1Byte IGIOffset_A;
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u1Byte IGIOffset_B;
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#endif
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}DIG_T,*pDIG_T;
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typedef struct _FALSE_ALARM_STATISTICS{
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u4Byte Cnt_Parity_Fail;
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u4Byte Cnt_Rate_Illegal;
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u4Byte Cnt_Crc8_fail;
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u4Byte Cnt_Mcs_fail;
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u4Byte Cnt_Ofdm_fail;
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u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
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u4Byte Cnt_Cck_fail;
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u4Byte Cnt_all;
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u4Byte Cnt_Fast_Fsync;
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u4Byte Cnt_SB_Search_fail;
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u4Byte Cnt_OFDM_CCA;
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u4Byte Cnt_CCK_CCA;
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u4Byte Cnt_CCA_all;
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u4Byte Cnt_BW_USC; //Gary
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u4Byte Cnt_BW_LSC; //Gary
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}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
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typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
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{
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DIG_TYPE_THRESH_HIGH = 0,
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DIG_TYPE_THRESH_LOW = 1,
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DIG_TYPE_BACKOFF = 2,
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DIG_TYPE_RX_GAIN_MIN = 3,
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DIG_TYPE_RX_GAIN_MAX = 4,
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DIG_TYPE_ENABLE = 5,
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DIG_TYPE_DISABLE = 6,
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DIG_OP_TYPE_MAX
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}DM_DIG_OP_E;
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/*
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typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
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{
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CCK_PD_STAGE_LowRssi = 0,
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CCK_PD_STAGE_HighRssi = 1,
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CCK_PD_STAGE_MAX = 3,
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}DM_CCK_PDTH_E;
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typedef enum tag_DIG_EXT_PORT_ALGO_Definition
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{
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DIG_EXT_PORT_STAGE_0 = 0,
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DIG_EXT_PORT_STAGE_1 = 1,
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DIG_EXT_PORT_STAGE_2 = 2,
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DIG_EXT_PORT_STAGE_3 = 3,
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DIG_EXT_PORT_STAGE_MAX = 4,
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}DM_DIG_EXT_PORT_ALG_E;
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typedef enum tag_DIG_Connect_Definition
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{
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DIG_STA_DISCONNECT = 0,
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DIG_STA_CONNECT = 1,
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DIG_STA_BEFORE_CONNECT = 2,
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DIG_MultiSTA_DISCONNECT = 3,
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DIG_MultiSTA_CONNECT = 4,
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DIG_CONNECT_MAX
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}DM_DIG_CONNECT_E;
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#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
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#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
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DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
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#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
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DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
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*/
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typedef enum tag_PHYDM_Pause_Type {
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PHYDM_PAUSE = BIT0,
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PHYDM_RESUME = BIT1
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} PHYDM_PAUSE_TYPE;
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typedef enum tag_PHYDM_Pause_Level {
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/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
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PHYDM_PAUSE_LEVEL_0 = 0,
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PHYDM_PAUSE_LEVEL_1 = 1,
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PHYDM_PAUSE_LEVEL_2 = 2,
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PHYDM_PAUSE_LEVEL_3 = 3,
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PHYDM_PAUSE_LEVEL_4 = 4,
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PHYDM_PAUSE_LEVEL_5 = 5,
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PHYDM_PAUSE_LEVEL_6 = 6,
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PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
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} PHYDM_PAUSE_LEVEL;
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#define DM_DIG_THRESH_HIGH 40
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#define DM_DIG_THRESH_LOW 35
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#define DM_FALSEALARM_THRESH_LOW 400
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#define DM_FALSEALARM_THRESH_HIGH 1000
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#define DM_DIG_MAX_NIC 0x3e
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#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c
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#define DM_DIG_MAX_OF_MIN_NIC 0x3e
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#define DM_DIG_MAX_AP 0x3e
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#define DM_DIG_MIN_AP 0x1c
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#define DM_DIG_MAX_OF_MIN 0x2A //0x32
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#define DM_DIG_MIN_AP_DFS 0x20
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#define DM_DIG_MAX_NIC_HP 0x46
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#define DM_DIG_MIN_NIC_HP 0x2e
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#define DM_DIG_MAX_AP_HP 0x42
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#define DM_DIG_MIN_AP_HP 0x30
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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#define DM_DIG_MAX_AP_COVERAGR 0x26
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#define DM_DIG_MIN_AP_COVERAGE 0x1c
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#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
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#define DM_DIG_TP_Target_TH0 500
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#define DM_DIG_TP_Target_TH1 1000
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#define DM_DIG_TP_Training_Period 10
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#endif
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//vivi 92c&92d has different definition, 20110504
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//this is for 92c
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
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#define DM_DIG_FA_TH0 0x80//0x20
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#else
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#define DM_DIG_FA_TH0 0x200//0x20
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#endif
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#else
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#define DM_DIG_FA_TH0 0x200//0x20
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#endif
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#define DM_DIG_FA_TH1 0x300
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#define DM_DIG_FA_TH2 0x400
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//this is for 92d
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#define DM_DIG_FA_TH0_92D 0x100
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#define DM_DIG_FA_TH1_92D 0x400
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#define DM_DIG_FA_TH2_92D 0x600
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#define DM_DIG_BACKOFF_MAX 12
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#define DM_DIG_BACKOFF_MIN -4
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#define DM_DIG_BACKOFF_DEFAULT 10
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#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
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#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
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#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
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#define RSSI_OFFSET_DIG 0x05
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VOID
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ODM_ChangeDynamicInitGainThresh(
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IN PVOID pDM_VOID,
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IN u4Byte DM_Type,
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IN u4Byte DM_Value
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);
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VOID
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ODM_Write_DIG(
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IN PVOID pDM_VOID,
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IN u1Byte CurrentIGI
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);
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VOID
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odm_PauseDIG(
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IN PVOID pDM_VOID,
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IN PHYDM_PAUSE_TYPE PauseType,
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IN PHYDM_PAUSE_LEVEL pause_level,
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IN u1Byte IGIValue
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);
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VOID
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odm_DIGInit(
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IN PVOID pDM_VOID
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);
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VOID
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odm_DIG(
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IN PVOID pDM_VOID
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);
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VOID
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odm_DIGbyRSSI_LPS(
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IN PVOID pDM_VOID
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);
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VOID
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odm_FalseAlarmCounterStatistics(
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IN PVOID pDM_VOID
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);
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VOID
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odm_PauseCCKPacketDetection(
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IN PVOID pDM_VOID,
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IN PHYDM_PAUSE_TYPE PauseType,
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IN PHYDM_PAUSE_LEVEL pause_level,
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IN u1Byte CCKPDThreshold
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);
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VOID
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odm_CCKPacketDetectionThresh(
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IN PVOID pDM_VOID
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);
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VOID
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ODM_Write_CCK_CCA_Thres(
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IN PVOID pDM_VOID,
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IN u1Byte CurCCK_CCAThres
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);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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VOID
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odm_MPT_DIGCallback(
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PRT_TIMER pTimer
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);
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VOID
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odm_MPT_DIGWorkItemCallback(
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IN PVOID pContext
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);
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
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VOID
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odm_MPT_DIGCallback(
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IN PVOID pDM_VOID
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);
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#endif
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#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
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VOID
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ODM_MPT_DIG(
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IN PVOID pDM_VOID
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);
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#endif
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#endif
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