108 lines
3.9 KiB
C
108 lines
3.9 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2013 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*******************************************************************************/
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#ifndef __RTL8821A_SPEC_H__
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#define __RTL8821A_SPEC_H__
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#include <drv_conf.h>
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// This file should based on "hal_com_reg.h"
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#include <hal_com_reg.h>
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// Because 8812a and 8821a is the same serial,
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// most of 8821a register definitions are the same as 8812a.
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#include <rtl8812a_spec.h>
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//============================================================
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// 8821A Regsiter offset definition
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//============================================================
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//============================================================
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// MAC register
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//============================================================
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//-----------------------------------------------------
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// 0x0000h ~ 0x00FFh System Configuration
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//-----------------------------------------------------
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//-----------------------------------------------------
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// 0x0100h ~ 0x01FFh MACTOP General Configuration
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//-----------------------------------------------------
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#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
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//-----------------------------------------------------
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// 0x0200h ~ 0x027Fh TXDMA Configuration
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//-----------------------------------------------------
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//-----------------------------------------------------
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// 0x0280h ~ 0x02FFh RXDMA Configuration
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//-----------------------------------------------------
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//-----------------------------------------------------
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// 0x0300h ~ 0x03FFh PCIe
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//-----------------------------------------------------
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//-----------------------------------------------------
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// 0x0400h ~ 0x047Fh Protocol Configuration
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//-----------------------------------------------------
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//-----------------------------------------------------
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// 0x0500h ~ 0x05FFh EDCA Configuration
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//-----------------------------------------------------
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//-----------------------------------------------------
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// 0x0600h ~ 0x07FFh WMAC Configuration
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//-----------------------------------------------------
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//============================================================
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// SDIO Bus Specification
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//============================================================
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//-----------------------------------------------------
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// SDIO CMD Address Mapping
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//-----------------------------------------------------
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//-----------------------------------------------------
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// I/O bus domain (Host)
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//-----------------------------------------------------
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//-----------------------------------------------------
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// SDIO register
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//-----------------------------------------------------
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#undef SDIO_REG_HCPWM1
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#define SDIO_REG_FREE_TXPG2 0x024
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#define SDIO_REG_HCPWM1 0x025
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//============================================================
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// Regsiter Bit and Content definition
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//============================================================
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//========================================================
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// General definitions
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//========================================================
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#define MACID_NUM_8821A 128
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#define SEC_CAM_ENT_NUM_8821A 64
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#define NSS_NUM_8821A 1
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#define BAND_CAP_8821A (BAND_CAP_2G | BAND_CAP_5G)
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#define BW_CAP_8821A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M)
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#endif /* __RTL8821A_SPEC_H__ */
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