462 lines
13 KiB
C
462 lines
13 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2013 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#include <rtw_odm.h>
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#include <hal_data.h>
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const char *odm_comp_str[] = {
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/* BIT0 */"ODM_COMP_DIG",
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/* BIT1 */"ODM_COMP_RA_MASK",
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/* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
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/* BIT3 */"ODM_COMP_FA_CNT",
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/* BIT4 */"ODM_COMP_RSSI_MONITOR",
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/* BIT5 */"ODM_COMP_CCK_PD",
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/* BIT6 */"ODM_COMP_ANT_DIV",
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/* BIT7 */"ODM_COMP_PWR_SAVE",
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/* BIT8 */"ODM_COMP_PWR_TRAIN",
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/* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
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/* BIT10 */"ODM_COMP_PATH_DIV",
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/* BIT11 */"ODM_COMP_PSD",
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/* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
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/* BIT13 */"ODM_COMP_RXHP",
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/* BIT14 */"ODM_COMP_MP",
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/* BIT15 */"ODM_COMP_CFO_TRACKING",
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/* BIT16 */"ODM_COMP_ACS",
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/* BIT17 */"PHYDM_COMP_ADAPTIVITY",
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/* BIT18 */"PHYDM_COMP_RA_DBG",
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/* BIT19 */"PHYDM_COMP_TXBF",
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/* BIT20 */"ODM_COMP_EDCA_TURBO",
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/* BIT21 */"ODM_COMP_EARLY_MODE",
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/* BIT22 */"ODM_FW_DEBUG_TRACE",
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/* BIT23 */NULL,
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/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
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/* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
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/* BIT26 */"ODM_COMP_CALIBRATION",
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/* BIT27 */NULL,
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/* BIT28 */"ODM_PHY_CONFIG",
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/* BIT29 */"BEAMFORMING_DEBUG",
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/* BIT30 */"ODM_COMP_COMMON",
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/* BIT31 */"ODM_COMP_INIT",
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/* BIT32 */"ODM_COMP_NOISY_DETECT",
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};
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#define RTW_ODM_COMP_MAX 33
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const char *odm_ability_str[] = {
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/* BIT0 */"ODM_BB_DIG",
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/* BIT1 */"ODM_BB_RA_MASK",
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/* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
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/* BIT3 */"ODM_BB_FA_CNT",
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/* BIT4 */"ODM_BB_RSSI_MONITOR",
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/* BIT5 */"ODM_BB_CCK_PD",
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/* BIT6 */"ODM_BB_ANT_DIV",
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/* BIT7 */"ODM_BB_PWR_SAVE",
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/* BIT8 */"ODM_BB_PWR_TRAIN",
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/* BIT9 */"ODM_BB_RATE_ADAPTIVE",
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/* BIT10 */"ODM_BB_PATH_DIV",
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/* BIT11 */"ODM_BB_PSD",
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/* BIT12 */"ODM_BB_RXHP",
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/* BIT13 */"ODM_BB_ADAPTIVITY",
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/* BIT14 */"ODM_BB_CFO_TRACKING",
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/* BIT15 */"ODM_BB_NHM_CNT",
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/* BIT16 */"ODM_BB_PRIMARY_CCA",
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/* BIT17 */"ODM_BB_TXBF",
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/* BIT18 */NULL,
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/* BIT19 */NULL,
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/* BIT20 */"ODM_MAC_EDCA_TURBO",
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/* BIT21 */"ODM_MAC_EARLY_MODE",
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/* BIT22 */NULL,
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/* BIT23 */NULL,
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/* BIT24 */"ODM_RF_TX_PWR_TRACK",
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/* BIT25 */"ODM_RF_RX_GAIN_TRACK",
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/* BIT26 */"ODM_RF_CALIBRATION",
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};
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#define RTW_ODM_ABILITY_MAX 27
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const char *odm_dbg_level_str[] = {
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NULL,
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"ODM_DBG_OFF",
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"ODM_DBG_SERIOUS",
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"ODM_DBG_WARNING",
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"ODM_DBG_LOUD",
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"ODM_DBG_TRACE",
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};
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#define RTW_ODM_DBG_LEVEL_NUM 6
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void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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int cnt = 0;
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u64 dbg_comp = 0;
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int i;
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rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_FLAG, &dbg_comp, NULL);
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DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
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for (i=0;i<RTW_ODM_COMP_MAX;i++) {
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if (odm_comp_str[i])
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DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
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(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
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}
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}
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inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
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{
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rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_FLAG, &comps, _FALSE);
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}
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void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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int cnt = 0;
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u32 dbg_level = 0;
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int i;
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rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_LEVEL, &dbg_level, NULL);
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DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
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for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
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if (odm_dbg_level_str[i])
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DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
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}
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}
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inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
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{
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rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_LEVEL, &level, _FALSE);
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}
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void rtw_odm_ability_msg(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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int cnt = 0;
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u32 ability = 0;
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int i;
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ability = rtw_phydm_ability_get(adapter);
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DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
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for (i=0;i<RTW_ODM_ABILITY_MAX;i++) {
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if (odm_ability_str[i])
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DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
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(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
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}
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}
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inline void rtw_odm_ability_set(_adapter *adapter, u32 ability)
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{
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rtw_phydm_ability_set(adapter, ability);
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}
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/* set ODM_CMNINFO_IC_TYPE based on chip_type */
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void rtw_odm_init_ic_type(_adapter *adapter)
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{
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &hal_data->odmpriv;
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u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
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rtw_warn_on(!ic_type);
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ODM_CmnInfoInit(odm, ODM_CMNINFO_IC_TYPE, ic_type);
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}
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void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
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{
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DBG_871X_SEL_NL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
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}
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#define RTW_ADAPTIVITY_EN_DISABLE 0
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#define RTW_ADAPTIVITY_EN_ENABLE 1
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void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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struct mlme_priv *mlme = &adapter->mlmepriv;
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &hal_data->odmpriv;
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DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_EN_");
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if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) {
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DBG_871X_SEL(sel, "DISABLE\n");
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} else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) {
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DBG_871X_SEL(sel, "ENABLE\n");
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} else {
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DBG_871X_SEL(sel, "INVALID\n");
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}
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}
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#define RTW_ADAPTIVITY_MODE_NORMAL 0
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#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
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void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_MODE_");
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if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) {
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DBG_871X_SEL(sel, "NORMAL\n");
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} else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) {
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DBG_871X_SEL(sel, "CARRIER_SENSE\n");
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} else {
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DBG_871X_SEL(sel, "INVALID\n");
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}
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}
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#define RTW_ADAPTIVITY_DML_DISABLE 0
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#define RTW_ADAPTIVITY_DML_ENABLE 1
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void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DML_");
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if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) {
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DBG_871X_SEL(sel, "DISABLE\n");
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} else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) {
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DBG_871X_SEL(sel, "ENABLE\n");
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} else {
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DBG_871X_SEL(sel, "INVALID\n");
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}
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}
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void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff);
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}
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void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
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{
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rtw_odm_adaptivity_ver_msg(sel, adapter);
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rtw_odm_adaptivity_en_msg(sel, adapter);
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rtw_odm_adaptivity_mode_msg(sel, adapter);
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rtw_odm_adaptivity_dml_msg(sel, adapter);
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rtw_odm_adaptivity_dc_backoff_msg(sel, adapter);
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}
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bool rtw_odm_adaptivity_needed(_adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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struct mlme_priv *mlme = &adapter->mlmepriv;
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bool ret = _FALSE;
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if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
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ret = _TRUE;
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return ret;
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}
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void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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rtw_odm_adaptivity_config_msg(sel, adapter);
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DBG_871X_SEL_NL(sel, "%10s %16s %16s %22s %12s\n"
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, "TH_L2H_ini", "TH_EDCCA_HL_diff", "TH_L2H_ini_mode2", "TH_EDCCA_HL_diff_mode2", "EDCCA_enable");
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DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n"
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, (u8)odm->TH_L2H_ini
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, odm->TH_EDCCA_HL_diff
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, (u8)odm->TH_L2H_ini_mode2
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, odm->TH_EDCCA_HL_diff_mode2
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, odm->EDCCA_enable
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);
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DBG_871X_SEL_NL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag");
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DBG_871X_SEL_NL(sel, "%-15x %-9x\n"
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, odm->Adaptivity_enable
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, odm->adaptivity_flag
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);
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}
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void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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odm->TH_L2H_ini = TH_L2H_ini;
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odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
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odm->TH_L2H_ini_mode2 = TH_L2H_ini_mode2;
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odm->TH_EDCCA_HL_diff_mode2 = TH_EDCCA_HL_diff_mode2;
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odm->EDCCA_enable = EDCCA_enable;
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}
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void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &(hal_data->odmpriv);
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DBG_871X_SEL_NL(sel,"RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
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HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
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}
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void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
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{
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
|
||
|
|
_irqL irqL;
|
||
|
|
|
||
|
|
switch(type)
|
||
|
|
{
|
||
|
|
case RT_IQK_SPINLOCK:
|
||
|
|
_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
|
||
|
|
{
|
||
|
|
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
|
||
|
|
_irqL irqL;
|
||
|
|
|
||
|
|
switch(type)
|
||
|
|
{
|
||
|
|
case RT_IQK_SPINLOCK:
|
||
|
|
_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_DFS_MASTER
|
||
|
|
VOID rtw_odm_radar_detect_reset(_adapter *adapter)
|
||
|
|
{
|
||
|
|
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||
|
|
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
|
||
|
|
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 0);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 1);
|
||
|
|
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1);
|
||
|
|
} else {
|
||
|
|
/* not supported yet */
|
||
|
|
rtw_warn_on(1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
VOID rtw_odm_radar_detect_disable(_adapter *adapter)
|
||
|
|
{
|
||
|
|
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||
|
|
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
|
||
|
|
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D)
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 0);
|
||
|
|
else if (pDM_Odm->SupportICType & ODM_RTL8821)
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
|
||
|
|
else
|
||
|
|
rtw_warn_on(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* called after ch, bw is set, chance to adjust parameter for different ch conditions */
|
||
|
|
VOID rtw_odm_radar_detect_enable(_adapter *adapter)
|
||
|
|
{
|
||
|
|
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||
|
|
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
|
||
|
|
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xc38, BIT23 | BIT22, 2);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x814, bMaskDWord, 0x04cc4d10);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xc8c, BIT23 | BIT22, 3);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xc30, 0xf, 0xa);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xcdc, 0xf0000, 4);
|
||
|
|
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x0152a400);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20);
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204);
|
||
|
|
} else {
|
||
|
|
/* not supported yet */
|
||
|
|
rtw_warn_on(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
rtw_odm_radar_detect_reset(adapter);
|
||
|
|
}
|
||
|
|
|
||
|
|
BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
|
||
|
|
{
|
||
|
|
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||
|
|
PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
|
||
|
|
BOOLEAN enable_DFS = FALSE;
|
||
|
|
BOOLEAN bypass = FALSE;
|
||
|
|
BOOLEAN radar_detected = FALSE;
|
||
|
|
|
||
|
|
static u8Byte last_tx_unicast = 0;
|
||
|
|
static u8Byte last_rx_unicast = 0;
|
||
|
|
static u8Byte throughput = 0;
|
||
|
|
int tp_th = ((*pDM_Odm->pBandWidth == ODM_BW40M) ? 45 : 20); /*refer AP team's testing number*/
|
||
|
|
|
||
|
|
throughput = (*(pDM_Odm->pNumTxBytesUnicast) - last_tx_unicast) + (*(pDM_Odm->pNumRxBytesUnicast) - last_rx_unicast);
|
||
|
|
last_tx_unicast = *(pDM_Odm->pNumTxBytesUnicast);
|
||
|
|
last_rx_unicast = *(pDM_Odm->pNumRxBytesUnicast);
|
||
|
|
|
||
|
|
if (throughput>>18 > tp_th) {
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D)
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xcdc, BIT8|BIT9, 0);
|
||
|
|
bypass = TRUE;
|
||
|
|
} else {
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D)
|
||
|
|
ODM_SetBBReg(pDM_Odm, 0xcdc, BIT8|BIT9, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
|
||
|
|
if (ODM_GetBBReg(pDM_Odm , 0xc84, BIT25))
|
||
|
|
enable_DFS = TRUE;
|
||
|
|
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
|
||
|
|
if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15))
|
||
|
|
enable_DFS = TRUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pDM_Odm->SupportICType & ODM_RTL8192D) {
|
||
|
|
if (ODM_GetBBReg(pDM_Odm , 0xcf8, BIT23))
|
||
|
|
radar_detected = TRUE;
|
||
|
|
} else if (pDM_Odm->SupportICType & ODM_RTL8821) {
|
||
|
|
if (ODM_GetBBReg(pDM_Odm , 0xf98, BIT17))
|
||
|
|
radar_detected = TRUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD
|
||
|
|
, ("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d\n"
|
||
|
|
, enable_DFS, radar_detected, bypass));
|
||
|
|
if (0)
|
||
|
|
DBG_871X("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d(throughput:%llu, tp_th:%d)\n"
|
||
|
|
, enable_DFS, radar_detected, bypass, throughput, tp_th);
|
||
|
|
|
||
|
|
if (enable_DFS && radar_detected)
|
||
|
|
rtw_odm_radar_detect_reset(adapter);
|
||
|
|
|
||
|
|
exit:
|
||
|
|
return (enable_DFS && radar_detected && !bypass);
|
||
|
|
}
|
||
|
|
#endif /* CONFIG_DFS_MASTER */
|
||
|
|
|